Key Responsibilities
Lead block/chip-level physical design activities from RTL to GDSII.
Work extensively in AMD flow, ensuring design compliance with AMDs methodology and quality standards.
Drive floorplanning, placement, CTS, routing, timing optimization, IR drop, and EM closure.
Collaborate with front-end, DFT, and physical verification teams to ensure seamless design integration.
Manage design execution timelines, track quality metrics, and guide team members on technical challenges.
Work on signoff for STA, LVS, DRC, and power verification using industry-standard EDA tools.
Provide mentoring, review, and technical guidance to junior PD engineers.

Required Skills & Experience
8+ years of hands-on experience in Physical Design at block or chip level.
Extensive experience with AMD flow is mandatory.
Proficiency in EDA tools such as Innovus, ICC2, PrimeTime, Voltus, RedHawk, and Calibre.
Robust understanding of timing analysis, power optimization, congestion management, and signal integrity.
Experience in advanced process nodes (7nm/5nm or below).
Excellent debugging and problem-solving skills.
Robust communication, leadership, and coordination skills.

📌 Physical Design Engineer Bengaluru
🏢 G.t.d Technologies
📍 Bengaluru