We are looking for an experienced Senior Physical Design Engineer with 5+ years of hands-on experience in VLSI Physical Design. The candidate will be responsible for executing and optimizing physical implementation activities from netlist to GDSII, with strong expertise in timing closure, PPA optimization, and physical signoff.
Key Responsibilities
- Perform end-to-end Physical Design implementation from Netlist to GDSII.
- Execute floorplanning, power planning, placement, CTS, routing, and optimization.
- Perform timing analysis and closure for setup and hold violations.
- Work on MMMC scenarios and optimize critical paths.
- Analyze and resolve congestion, timing, power, and area issues.
- Perform PPA optimization across implementation stages.
- Implement and debug ECOs for timing and functional requirements.
- Resolve physical violations including DRC, LVS, antenna, and density issues.
- Support IR drop and EM analysis and signoff activities.
- Work with STA, RTL, Synthesis, DFT and Physical Verification teams to resolve implementation issues.
- Contribute to flow and methodology improvements.
- Develop and use Tcl/Perl/Python scripts for automation and productivity improvement.
Required Skills
- 5+ years of relevant experience in Physical Design.
- Strong understanding of the complete PD flow.
- Hands-on experience with one or more of:
- Cadence Innovus
- Synopsys Fusion Compiler
- Synopsys ICC2
- Strong knowledge of:
- Floorplanning
- Power Planning
- Placement
- CTS
- Routing
- Timing Closure
- MMMC
- PPA Optimization
- ECO
- Physical Signoff
- Good understanding of STA and timing constraints.
- Knowledge of Low Power / Multi-Voltage implementation is an advantage.
- Good scripting skills in Tcl; Perl/Python is an added advantage.
Education
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related engineering discipline.