About Client

Our Client is a signal processing infrastructure company. they build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical workloads.

Our Client’s Silicon is their ground-up effort to build a new compute category.

About the Role

We need a strong RTL expert who can lead our silicon program to tapeout. You will be the technical bridge between our architecture and our design partner, owning every step from RTL freeze to GDSII handoff, working with our partners. You will also build and lead the RTL team of 5–7 engineers. This is a hands-on lead role. You write RTL, review RTL, run synthesis, and own the result. The architect defines what gets built. You own how it gets built.

Responsibilities

Translate the architecture specification into synthesizable SystemVerilog

Own the RTL coding standards, linting rules, and design methodology

Lead a team of 5-7 RTL engineers through the full design cycle

Own the synthesis flow (Design Compiler or Genus) and drive timing closure

Define and maintain SDC timing constraints





Review all RTL code submissions for correctness, synthesizability, and style

Coordinate with the outsource partner on GDSII handover (netlist, constraints, floorplan guidance)

Work closely with the verification team to resolve bugs and achieve coverage closure

Requirements

Experience

4+ OR 7+ years of RTL design experience in SystemVerilog

At least 1 tapeout through to GDSII (not just RTL — you've seen the full flow)

Synthesis and timing closure experience (Design Compiler or Genus, PrimeTime or

Tempus)

Processor, DSP, or datapath-heavy design experience

Familiarity with advanced process nodes (28nm class or below)

Strong code review skills, you can spot timing hazards, FSM issues, and non-synthesizable patterns in review

Comfortable leading a small team while remaining hands-on

Valuable to have

VLIW or vector processor design experience

Experience with deterministic/real-time architectures (no caches, fixed latencies)

Formal verification awareness (writing SVA, working with formal tools)

FPGA prototyping experience (Vivado)

Work Mode: 5 days WFO

Location: Bangalore

📌 Senior OR Lead RTL Design Engineer (Bengaluru)
🏢 Zyoin Group
📍 Bengaluru