Develop full-custom memory layouts for SRAM, ROM, Register File, and other memory-related blocks.Work on layout of bit cells, row/column logic, sense amplifiers, pre-charge circuits, decoders, drivers, and peripheral circuits .Perform floor planning, placement, routing, matching, shielding, and power planning.Ensure proper implementation of

DRC, LVS, ERC and other physical verification checks .Debug and resolve layout and verification issues.Work closely with circuit/design engineers to understand schematics and implement optimized layouts.Support

PEX and post-layout verification activities.Follow layout methodologies for area, performance, matching, reliability, and manufacturability .Support tape-out activities and ensure timely delivery of layout blocks.

Required Skills

Robust experience in





Memory Layout / Custom Layout .4-8 years of relevant experience in memory layout.Hands-on experience with

Cadence Virtuoso .Good understanding of

DRC/LVS/ERC and physical verification.Experience with

Calibre or equivalent verification tools.Good understanding of CMOS devices, matching techniques, common-centroid layout, shielding, guard rings, and routing.Experience with advanced technology nodes is an added advantage.Ability to interpret schematics and work independently on layout implementation.

Preferred Experience

SRAM / ROM / Register File / Memory Compiler layout.Advanced-node memory layout experience.Experience with

TSMC / Samsung / GlobalFoundries technologies.Experience working on full-custom analog/mixed-signal environments.

📌 Memory Layout Engineer (Mumbai)
🏢 smartsoc solutions
📍 Mumbai