There is an opening for Lead PCB Schematic Design Engineer (grade T3) in the High Speed SERDES Physical Layer Electrical Validation team at Cadence Design Systems, Bangalore. The role is intended for candidates with direct experience in this domain in the range of at least 4 years.
Why choose Cadence Design Systems? These roles offer the opportunity to work on the post silicon electrical validation of various cutting edge high speed SERDES and Die to Die designs. Apart from the challenging work and chance for gain deep knowledge in these technologies, Cadence also offers attractive compensation packages.
What we are looking for in potential candidates is listed below.
Minimum Qualifications
- BTECH/MTECH in in an Electronics stream with experience greater than or equal to 4 years in PCB Schematic Design
- Involvement in PCB designs related to AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc
Preferred Qualifications
- Experience in Cadence design systems schematic design tools flows