We are looking for a Lead Physical Design Engineer with strong full-chip Physical Design experience and deep expertise in Cadence Innovus to drive implementation and sign-off of complex SoCs.
Key Responsibilities
- Own full-chip Physical Design from netlist to tape-out.
- Drive floorplanning, power planning, placement, CTS, routing and optimization.
- Strong hands-on experience with Cadence Innovus for implementation and PPA optimization.
- Drive timing closure, congestion optimization and ECO implementation.
- Work closely with STA, RTL, DFT, synthesis and sign-off teams to resolve implementation issues.
- Analyze and resolve setup/hold, SI, IR drop, congestion and DRC/LVS issues.
- Support MMMC implementation and sign-off across multiple modes/corners.
- Develop and debug Tcl-based automation and PD flows.
- Drive physical design quality, methodology and tape-out readiness.
Required Skills
- 6–12 years of ASIC Physical Design experience.
- Proven full-chip SoC implementation experience.
- Strong hands-on expertise in Cadence Innovus.
- Strong understanding of STA, CTS, routing, timing closure and physical verification.
- Experience with advanced technology nodes and complex SoCs preferred.
- Solid scripting skills in Tcl/Perl/Python.
- Experience with PrimeTime, Voltus, Tempus/Calibre or equivalent sign-off tools is preferred.