Lead DFT Engineer

nLocation: Bangalore

nExperience: 8+ Years

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nWe are looking for an experienced Lead DFT Engineer with robust expertise in Design-for-Test (DFT), ATPG, and MBIST, along with hands-on experience using Cadence tools.

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nKey Responsibilities

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- Lead DFT architecture, implementation, and verification for complex SoC designs.
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- Drive scan insertion, ATPG pattern generation, coverage analysis, and test pattern debugging.
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- Implement and verify MBIST, memory test architectures, and test controllers.
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- Perform DFT rule checks (DRC), scan chain analysis, and test coverage optimization.
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- Collaborate with RTL, Physical Design, and Verification teams to resolve DFT-related issues.
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- Support DFT sign-off, test pattern validation, and production test readiness.
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nMust-Have Skills

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- 8+ years of hands-on DFT engineering experience.
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- Strong expertise in ATPG and MBIST.
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- Hands-on experience with Cadence DFT tools.
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- Expertise in scan insertion, scan compression, DFT architecture, and test coverage analysis.
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- Strong debugging, problem-solving, and cross-functional collaboration skills.
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nPreferred Skills

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- Experience with full-chip SoC DFT implementation and silicon validation.
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- Knowledge of JTAG, boundary scan, and IEEE 1500/1687 standards.
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- Experience supporting DFT sign-off and manufacturing test requirements.
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📌 Lead DFT Engineer (Bengaluru)
🏢 LanceSoft
📍 Bengaluru