Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions to global customers. The organization combines deep expertise across the semiconductor value chain with a strong focus on high performance, quality, and faster time-to-market. Its engineering team covers the full design spectrum, including analog circuit design, custom layout, RTL design, verification, physical design, embedded design, and full-chip/SoC backend.

SiMaxTech works across a wide range of technology nodes, from mature processes like 65nm and 28nm to advanced nodes such as 7nm, 5nm, 3nm, and emerging nodes like 2nm and 18A. Guided by a vision to be a preferred global partner, the company emphasizes continuous learning, innovation, and a customer-centric approach focused on reliability and scalability.

Role Description The Lead Analog Layout Engineer is a full-time, in office role based in Bengaluru South. This role involves owning and executing complex analog and mixed-signal layout for high-performance ICs, including floorplanning, device placement, routing, and optimization in advanced technology nodes.

The Lead Analog Layout

Engineer will collaborate closely with analog circuit designers to translate schematics into robust layouts, manage design constraints, and ensure compliance with performance, area, and reliability targets.



Day-to-day responsibilities include running and reviewing physical verification (DRC, LVS, ERC, and reliability checks), resolving layout-related issues, and driving design closure. The role also includes mentoring layout engineers, contributing to layout methodologies and best practices, and coordinating with cross-functional teams to support end-to-end chip development.

Qualifications

- Strong skills in layout-related domains, including Layout Design and Custom Analog Layout for complex blocks and full-chip integration.
- Solid expertise in circuit-level domains such as Circuit Design, Analog, and Analog Circuits, with the ability to interpret schematics and understand device behavior and constraints.
- Hands-on experience with Physical Verification, including DRC, LVS, ERC, and reliability checks (EM, IR drop), and closure on advanced technology nodes.
- Proficiency with industry-standard EDA tools for analog layout and verification (e.g., Cadence Virtuoso, Mentor/Siemens Calibre, Synopsys tools).
- Experience in advanced and mature process technologies (e.g., 65nm and below, with exposure to 7nm/5nm/3nm or similar) and awareness of layout challenges at scaled nodes.
- Ability to lead projects, mentor junior layout engineers, and collaborate effectively with circuit design, verification, and physical design teams.
- Strong analytical and problem-solving skills, attention to detail, and ability to work on-site in a fast

📌 Lead Analog Layout Engineers (India)
🏢 SiMaxTech
📍 India