Title: IP Logic Design Lead

Location: Bengaluru

About Company

We are a premium semiconductor design services company headquartered in Bangalore, India. We specialize in the development and delivery of complex Analog and Mixed-Signal IP solutions for leading semiconductor companies worldwide.

Our vision is to become the industry& most trusted partner for turnkey Analog IP development by combining deep technical expertise, execution excellence, and a customer-centric approach. We focus on solving some of the most challenging problems in semiconductor design, from IP migration and process-node portability to performance optimization, feature enhancements, and next-generation IP creation.

We expertise runs across multiple IP types such as:

High-Speed Serial IPs (SerDes, PCIe, Ethernet)

Memory and Parallel Interface IPs (DDR, LPDDR, HBM)

Die-to-Die and Chiplet Connectivity IPs (UCIe)

Infrastructure and Linear IPs (PLL, DLL, LDO, Voltage Regulators, GPIO, Clocking

Solutions)

Position Overview

We are seeking a highly motivated Analog Engineers to contribute to the development and delivery of world-class Analog, Mixed-Signal, and Interface IP solutions for leading semiconductor customers.

Key Responsibilities

 Lead the small Analog IP RTL design team.

 Implement the RTL Design from (A-specs) architectural specifications.

 Lead and execute IP RTL integration, IP level quality sign-off.





 Perform the basic quality checks such as functionality, lint, CDC, and synthesis checks.

 Define RTL design methodologies, coding standards, simulation flows, and debug processes.

 Partner with Design Verification team to develop verification strategies and analyze failures.

 Support SoC integration activities, and resolve IP-level issues.

 Provide technical leadership across verification, physical design, and SoC teams to ensure successful IP execution and delivery.

Minimum Qualifications

 Bachelor’s degree in Electrical Engineering with 8-10 years of RTL development experience.

 Experience with industry-standard protocols and PCIe/DDR/UCIE IP architecture.

 Solid expertise in SystemVerilog, RTL coding, and advanced digital design techniques.

 Proven experience in clock domain crossing (CDC), microarchitecture/simulation debug, and static timing analysis.

 Hands-on experience with LINT, CDC, RDC, synthesis, timing analysis, regression, and code coverage tools.

 Knowledge of AMBA, PCIe, UCIe, and DDR protocols and standards.

Desired Qualifications

 Knowledge of Analog/Digital interface, Analog IP DFX, and Analog block training would be great advantage

"analog IP"

PCIe

DDR

AMBA

UCIe

"System Verilog"

RTL Coding

LINT

CDC

RDC sythesis

Contact: Sumit S. B.

Mulya Technologies [email protected]

📌 IP Logic Design Lead (Bangalore Metropolitan Area)
🏢 Mulya Technologies
📍 Bangalore Metropolitan Area