- 7–12 years of hands-on experience in DFT implementation, ATPG and MBIST for complex SoCs.
- Strong experience in DFT architecture, insertion, verification and sign-off at full-chip level.
- Experience with scan chain insertion and compression using Tessent across multi-clock digital logic.
- Strong experience in ATPG pattern generation, fault simulation and coverage analysis.
- Hands-on experience with MBIST for internal SRAMs, FIFOs and memory macros.
- Experience with DFT integration of PHYs and third-party IPs, including DFT boundary conditions and DFT port connectivity.
- Experience with BIST and bus isolation, including PCS/PMA or similar high-speed interface blocks.
- Experience integrating IEEE 1149.1 JTAG controllers and boundary scan.
- Good understanding of scan architecture, test modes, test compression, clock/reset handling and DFT constraints.
- Experience in DFT verification, coverage closure, pattern debugging and sign-off.
- Design, Verification and IP teams to resolve DFT issues and support tape-out.
Preferred
- Experience with Tessent DFT/ATPG/MBIST flows.
- Experience with automotive SoCs and ISO 26262-related test requirements is an advantage.
- Experience with SerDes/PHY DFT integration is highly preferred.
- Valuable scripting skills in Tcl/Python/Perl for DFT automation.