In this role, you will own and drive Design for Test (DFT) strategy, architecture, and implementation across the full chip lifecycle.

Responsibilities

Execute and support Design-for-Test (DFT) activities, including Scan Insertion, ATPG, and OCC Integration.Perform DRC debugging, test coverage analysis, and simulation debugging across different stages of the DFT flow.Analyze and resolve issues related to testability, fault coverage, and pattern generation.Work with advanced DFT methodologies such as SSN, IJTAG, ICL, and PDL.Collaborate with cross-functional teams to ensure seamless DFT integration and productive issue resolution.Drive continuous improvements in DFT flows, methodologies, and debugging efficiency.

Experience: 3 to 8 yrs

Required Skills: Key Responsibilities:Define and implement DFT architecture for large, complex SoCs/ASICsOwn end-to-end DFT strategy and execution including Scan, ATPG, MBIST, LBIST, JTAG, and Boundary ScanPerform Scan insertion, ATPG pattern generation, compression,



and fault gradingDevelop and maintain DFT specifications and ensure compliance throughout the design cycleIntegrate and verify DFT logic at RTL and gate-level (GLS)Collaborate with verification teams for pattern simulation, validation, and debugWork closely with physical design teams to meet timing, power, and area constraintsDebug silicon bring-up issues and support ATE test pattern validationDrive improvements in DFT methodologies and flowsMentor junior engineers and provide technical leadershipStrong expertise in Scan, ATPG, BIST (MBIST/LBIST), JTAG/Boundary Scan, and compression techniquesHands-on experience with DFT tools such as Synopsys DFT Compiler, Tetramax, Tessent, or equivalentSolid understanding of RTL design, synthesis, and verification flowsFamiliarity with STA and physical design constraints related to DFTExperience in silicon bring-up and ATE test pattern generationStrong debugging and analytical skills

📌 DFT Engineer (Mumbai)
🏢 smartsoc solutions
📍 Mumbai