Design Verification Engineer (Vasanth Nagar)

Design Verification Engineer (Vasanth Nagar)

30 Sep
|
ACL Digital
|
Vasanth Nagar

30 Sep

ACL Digital

Vasanth Nagar

Design Verification Engineer - Senior / Lead / Sr. Lead

Must have positive knowledge on the verification flows.

Excellent hands-on debug skills and problem solving attitude..

Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC

Experience of working on Functional Verification, SoC Verification, Emulation

Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language.

OVM/UVM Methodology knowledge and experience

Must have good communication skills and the ability to work in a team environment.

Preferably having experience in architecture such as x86 or ARM domain based SOCs having SOC/IP performance verification background is added plus

Experience: 4 to 12 Years

Location: Bangalore / Hyderabad

Work Mode: Work from Office (WFO)

📌 Design Verification Engineer (Vasanth Nagar)
🏢 ACL Digital
📍 Vasanth Nagar

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