Job DescriptionRTL Design Engineer NExperience: 7–20+ Years NLocation: Bangalore NRole: Senior / Lead / Principal RTL Design Engineer NJob OverviewnWe are looking for experienced RTL Design Engineers with a strong background in Microarchitecture and Digital Design to work on complex semiconductor designs. The ideal candidate should have robust hands-on experience taking designs from microarchitecture/specification through RTL implementation, verification, synthesis and sign-off. NKey Responsibilitiesn N Understand and contribute to microarchitecture specifications and design requirements. N Translate microarchitecture into high-quality, synthesizable RTL using Verilog/SystemVerilog. N Design and implement complex IP, subsystem, SoC, CPU/GPU or processor blocks. N Participate in microarchitecture definition, design reviews and RTL architecture discussions. N Develop optimized RTL considering performance, power, area (PPA) and design complexity. N Work closely with Architecture, Verification, Physical Design and STA teams. N Perform RTL simulation, debugging and functional issue resolution. N Support lint, CDC, synthesis, STA and other design-quality checks. N Analyze and resolve timing, area, power and functional issues. N Drive design closure and support integration of RTL blocks into larger SoC designs.



N Mentor junior engineersand contribute to RTL coding standards and design methodologies. NnRequired Skills Nn 7–20+ years of experience in RTL Design / Digital Design. N Strong hands-on experience with Verilog/SystemVerilog. N Strong understanding ofMicroarchitecture and Digital Logic Design. N Experience in designingcomplex IP/SoC/subsystem blocks. N Good understanding of ASIC design flow from specification to implementation. N Strong knowledge of RTL coding, synthesis, lint, CDC and STA. N Experience with PPA optimization and timing closure. N Strong debugging and problem-solving skills. N Experience working withcross-functional teams including DV, Architecture and Physical Design. NnPreferred / Good to Have Nn Experience with CPU, GPU, AI/ML accelerators, interconnects or high-speed interfaces. N Experience in ARM/processor-based SoC designs. N Knowledge of low-power design methodologies. N Experience with formal verification and design-quality checks. N Experience leading RTL design teams or mentoring engineers. NnCandidate Profile NCandidates should have a strong microarchitecture foundation, excellent RTL coding skills, and experience owning complex blocks from microarchitecture through RTL and design closure.

📌 Senior / Lead / Principal Rtl Design Engineer (Vasanthanagar)
🏢 Leadsoc Technologies
📍 Vasanthanagar