Remote: Hybrid

Job Description( nStaff DFT EngineernThe 10 Hottest Semiconductor Startups Of 2025 (So Far) nnnn1nner nnLocation: Greater Bengaluru Area (Hybrid-2 days office,3 days-home) or Remote (any where in I nnndia nAbout Com npany:EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI sys nntems. nnDeveloping silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote enviro nnnments. nAs the Design for Test (DFT) Senior staff, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge dep nnloyment. nKey Respons nibilitiesArchitectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs,



including Hierarchical DFT, Scan compression, a nnnd MBIST. nEdge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge dat nna centers. nImplementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and nnLogic BIST. nCross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and p nnower impact. nPost-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimi nnze test time. nTechnica nl RequirementsExperience: 7-10 years in DFT, with at least 2 years in a leadership or p nnrincipal role. nTools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or nnCadence Modus). nMemory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities and boundary scan nn(IEEE 1149.1/6). nAdvanced Nodes: Proven track record with FinFET nodes (7nm nn, 5nm, or below). nLow Power: Experience managing DFT in multi-voltage/power-gated designs—crucial fo nnr edge neffinciency.nContactnUdaynmudanMulya Technologies n"Mining the K nowledge Community"

📌 Staff DFT Engineer (Aurangabad)
🏢 EnCharge AI
📍 Aurangabad