Senior STA Engineer

Experience: 5–10 Years
Job Type: Full-Time
Industry: Semiconductor / VLSI

Job Summary

We are looking for a Senior STA Engineer with robust experience in Static Timing Analysis, timing closure, and ASIC/SoC design flows.

Key Responsibilities

- Perform Static Timing Analysis (STA) and timing signoff.
- Analyze and resolve setup, hold, recovery, and removal violations.
- Handle MMMC, SDC constraints, OCV/AOCV/POCV, and CPPR.
- Drive timing closure across synthesis, placement, CTS, and routing stages.
- Debug timing reports and implement timing ECOs.
- Work closely with RTL, Physical Design, DFT, and Signoff teams.
- Develop automation scripts using Tcl/Python/Perl.

Required Skills

- 5–10 years of hands-on STA/Timing Closure experience.
- Strong knowledge of SDC, MMMC, clock analysis, and timing constraints.
- Experience with Synopsys PrimeTime or Cadence Tempus.
- Good understanding of ASIC/SoC and physical design flows.
- Strong analytical and problem-solving skills.

Pay: ₹1,500,000.00 - ₹2,000,000.00 per year

Benefits:

- Flexible schedule
- Paid sick time
- Paid time off

Work Location: In person

📌 Senior STA Engineer (India)
🏢 THINSIL
📍 India