Design Lead
Chennai, Tamil Nadu
Job Summary
We are seeking an experienced FPGA Design Engineer with strong expertise in AMD Versal/Zynq UltraScale+ FPGA devices and hands-on experience in implementing high-speed networking solutions. The ideal candidate will be responsible for architecting, designing, implementing, and optimizing FPGA-based systems for real-time, high-performance networking applications.
The candidate will play a key role in developing next-generation FPGA-based packet processing platforms, supporting hardware bring-up activities, and driving performance optimization for 400GbE-class networking solutions.
Key Responsibilities
Architecture & Design
Define and develop end-to-end FPGA architectures for:
- 400GbE Ethernet datapath solutions
- PCIe Gen5 x16 subsystems
- High-performance DMA architectures
- Multi-queue packet processing frameworks
- RSS (Receive Side Scaling) hashing engines
- SmartNIC and packet acceleration functionalities
- High-speed buffering and traffic management architectures
Design and implement hardware support for:
- Ethernet MAC integration
- VLAN and QinQ processing
- E-Tag insertion/removal
- MPLS, GRE, VXLAN, ERSPAN, and GTP-U packet parsing
- Flow classification and packet steering
RSS & Queue Management
- Design and implement RSS hashing engines using:
- - Toeplitz Hash
- Symmetric Toeplitz Hash
- Custom hash algorithms
- Develop scalable queue management and packet steering architectures.
- Optimize flow affinity and packet ordering mechanisms.
- Analyze and improve packet distribution efficiency across processing cores.
Verification, Testing & Debugging
- Develop simulation environments, verification plans, and testbenches.
- Perform functional verification and hardware validation on evaluation and custom boards.
- Conduct FPGA bring-up and system-level integration testing.
- Debug FPGA designs using:
- - Integrated Logic Analyzer (ILA)
- Vivado Hardware Manager
- Oscilloscopes
- Logic Analyzers
- Protocol Analyzers
- Drive timing closure and optimize:
- - Throughput
- Latency
- Resource utilization
- Power consumption
- Perform CDC, RDC, and timing analysis for complex FPGA designs.
Technical Leadership
- Drive FPGA design methodologies, coding standards, and development best practices.
- Lead architecture and design review meetings.
- Mentor and guide junior FPGA engineers.
- Participate in customer discussions, requirement analysis, and technical reviews.
- Collaborate with hardware, software, verification, and system engineering teams.
Skill Requirements
- Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
- 8 to 10 years of hands-on FPGA development experience.
- Robust experience with AMD Versal, Zynq UltraScale+, UltraScale+, or other high-end FPGA devices.
- Proficiency in Verilog/SystemVerilog RTL design and FPGA development flows.
- Strong background in embedded systems integration and FPGA-based system design.
- Experience implementing and debugging networking protocols and packet-processing pipelines.
- Solid understanding of:
- - AXI4 / AXI-Stream protocols
- XDMA
- DDR memory interfaces
- Frame buffers
- High-speed serial interfaces
- Multi-gigabit transceivers
- Strong knowledge of digital design fundamentals, board-level hardware design, and schematic interpretation.
- Experience with FPGA timing closure, CDC analysis, and performance optimization.
- Excellent debugging skills using Vivado tools, ChipScope/ILA, and lab instrumentation.
Preferred Qualifications
- Experience with 100GbE, 200GbE, or 400GbE Ethernet subsystems.
- Experience with PCIe Gen4/Gen5 subsystem integration.
- Exposure to SmartNIC, Network Packet Broker, or Network Acceleration platforms.
- Knowledge of RSS hashing, DMA architectures, and multi-queue networking solutions.
- Familiarity with DPDK, Linux networking stack, or packet-processing frameworks.
- Experience with hardware acceleration for networking, security, or telecom applications.
Other Requirements
📌 Design Lead (India)
🏢 HCLTech
📍 India