Job Requirements

Role Overview

Own day-to-day physical implementation of an assigned tile/block from netlist and constraints through routed, timing-clean and signoff-ready handoff. Candidates must demonstrate real implementation ownership rather than only flow execution or monitoring.

Key Responsibilities

- Validate netlist, libraries, constraints and floorplan inputs; identify readiness gaps

- Execute floorplanning, power planning, placement, CTS, routing and post-route optimisation

- Analyse congestion, utilisation, clock skew/latency, timing paths and route quality

- Fix setup/hold, transition, capacitance, fanout, noise and design-rule violations

- Generate and implement timing/physical ECOs and verify closure across required modes and corners

- Support extraction, STA, LEC, physical verification and IR/EM readiness checks

- Maintain run summaries, QoR comparisons, issue logs and closure status

- Work closely with tile lead, STA, RTL, DFT and integration teams to resolve dependencies

Required Skills & Expertise

- 3-8 years of relevant ASIC physical design experience with hands-on tile/block PnR work





- Experience with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler

- Practical knowledge of floorplanning, placement, CTS, routing and optimisation

- Ability to read timing reports and perform setup/hold debugging using PrimeTime and/or Tempus

- Familiarity with parasitic extraction using StarRC or equivalent

- Working knowledge of LEC and physical verification concepts

- Robust problem-solving, ownership and communication skills

Experience Calibration

- 3-5 years: Must independently execute major PnR stages, analyse reports and close common timing/physical violations with review support

- 6-8 years: Must independently own full tile closure, drive ECO convergence, review QoR, manage dependencies and guide junior engineers

Preferred Skills

- Exposure to RedHawk/Voltus and Calibre/Pegasus-class signoff checks

- TCL scripting capability; Python is an advantage

- Experience on advanced-node designs without sharing proprietary design information

Education

BE/BTech/MTech in Electronics, Electrical Engineering or a related discipline

📌 Senior Engineer (Hyderabad)
🏢 Quest Global
📍 Hyderabad