Company Description

Cadence is a global leader in digital Design technologies & AI, driving innovation in engineering design for silicon and systems. Through its Intelligent System Design™ strategy, Cadence delivers cutting-edge solutions that empower leading semiconductor and systems companies to create next-generation products for markets including computing, automotive, aerospace, robotics, and life sciences. Recognized as one of the world’s top 100 best-managed companies by the Wall Street Journal in 2024, Cadence provides solutions that enable limitless innovation opportunities.

For more information, visit www.cadence.com.

Role Description

We are seeking a driven and passionate individuals to join Cadence as a Lead/Principal/Sr.

Principal Product

Engineer. In this full-time, on-site role located in Bengaluru office. Several positions are available, each tailored to different levels of expertise and experience. You will learn & lead the development, optimization, and deployment of advanced engineering design solutions.

Your responsibilities will include designing and validating electronic systems, collaborating with cross-functional teams, developing and sustaining methodologies, and supporting key customers. You will also function as a technical leader driving critical projects, identifying and solving design challenges, and contributing to the continuous advancement of our product offerings.

Qualifications

▸ BE, MS in Electrical Engineering or related discipline

▸ 6–9 years of deep,



hands-on experience in ASIC physical design and/or EDA product engineering, with a demonstrable track record of shipping designs or product improvements.

▸ Expert-level understanding of the full RTL-to-GDSII flow: synthesis, floor-planning, placement, CTS, routing, static timing analysis, and physical sign-off.

▸ Proven experience with timing closure and PPA optimization at 16nm and below — including 10nm, 7nm, 5nm,3nm and 2nm FinFET processes.

▸ Deep proficiency with Cadence Innovus Implementation System, Tempus Timing Signoff Solution, and Genus Synthesis Solution; familiarity with Pegasus Physical Verification is a strong asset.

▸ Advanced expertise in static timing analysis: multi-mode multi-corner (MMMC), POCV/AOCV, hold-time optimization, and clock domain crossing (CDC) methodology.

▸ Thorough understanding of hierarchical design methodologies — interface timing modeling (ITM/ETM), black-box flows, and top-level integration.

▸ Extensive knowledge of low-power design: IEEE 1801 UPF, multi-voltage domains, power gating, retention strategies, and dynamic voltage/frequency scaling.

▸ Robust scripting and automation skills: Tcl (advanced), Perl, Python, and Shell; experience building reusable flow infrastructure is highly valued.

▸ Demonstrated leadership in technical problem-solving with an organized, data-driven approach and the ability to influence cross-functional teams.

▸ Excellent communication skills — able to present complex technical content clearly to executive stakeholders, customers, and R&D; partners alike.

📌 Principal Product Engineer (Bengaluru)
🏢 Cadence
📍 Bengaluru