We are looking for a Lead SoC Verification Engineer with strong expertise in SystemVerilog, UVM and high-speed protocols to drive verification of complex, high-performance SoCs.
Key Responsibilities
- Lead block, subsystem and SoC-level verification for complex ASIC/SoC designs.
- Develop scalable SystemVerilog/UVM testbenches, environments, sequences and scoreboards.
- Define verification strategy, test plans and coverage goals.
- Develop functional, stress and corner-case scenarios for high-speed interfaces and protocols.
- Debug complex simulation failures using VCS/Verdi or equivalent tools.
- Drive functional and code coverage closure and verification sign-off.
- Work closely with RTL, Architecture, DFT, Performance and Post-Silicon teams to resolve design issues.
- Contribute to verification methodology,
automation and reusable VIP/UVM components.
- Mentor verification engineers and provide technical leadership across projects.
Required Expertise
- 8–12 years of hands-on SoC/ASIC verification experience.
- Robust SystemVerilog and UVM expertise.
- Strong experience with high-speed protocols such as PCIe, CXL, Ethernet, DDR/LPDDR, USB or similar.
- Solid understanding of SoC architecture, IP/subsystem integration and protocol verification.
- Experience with constrained-random verification, assertions and functional coverage.
- Strong debugging skills using VCS, Verdi or equivalent.
- Proficiency in Python/Perl/Tcl for verification automation.
- Strong communication, problem-solving and technical leadership skills.