3–10 yrs experience in Gate-Level Simulation
Strong knowledge of SystemVerilog and UVM.
Experience with VCS / Questa or similar simulation tools
Experience working with SoC/IP-level verification environments.
Good scripting skills in Python/Tcl/Perl
Required Candidate profile
Mandatory Skills: GLS, Gate-Level Simulation, SystemVerilog, SDF, VCS/Questa
Valuable to Have: UVM, Python/Tcl/Perl
Interested can share a resume at
[email protected]
📌 GLS Verification Engineer (Bengaluru)
🏢 incise infotech
📍 Bengaluru