5+ years of hands-on experience in ASIC/So C DFT implementation and verification. Strong expertise in Synopsys DFT tools, with mandatory hands-on experience in SMS and SEQ insertion. Strong experience in Scan insertion, Scan compression, DFT DRC debugging, and coverage closure.
Hands-on experience with ATPG, including stuck-at and transition fault pattern generation and debugging. Positive knowledge of MBIST, JTAG/Boundary Scan, test clocks, resets, and multi-clock DFT architectures. Proficiency in TCL/Perl/Python/Shell scripting and experience supporting DFT flows through tape-out.