Position: DDR (BB612FT RM 4439)

Required skillset:

- Hands-on experience and very good understanding of DDRPHY architecture, DFI protocol and Jedec standards for latest Gens.
- Experience in verification and general computational logic design/verification concepts.
- Working Experience on LPDDR5/LPDDR4 (Must)
- Expertise in Verilog/System Verilog and UVM/OVM.
- Robust debugging, Analytical and problem-solving skills.
- Experience in Scripting languages like Perl would be a plus.
- Post-si bring-up and HW-SW debug experience would be a plus.

Responsibilities:

- Testplan to Vector Delivery all the assigned task ownership and closure.
- Debug of regression signatures and identifying bug fixes.
- Responsible for Quality sign-off and required documentation.




- Debug and root cause SS/SOC/post silicon issues in collaboration with Design teams.
- Understanding of standard bus protocols like AHB, AXI protocols would be a plus.
- Having the right attitude to learn and quickly adapt to changing industry trends

Job Category: Others

Job Type: Full Time

Job Location: Bangalore

Experience: 6-12 years

Notice period: 0-30 days

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 DDR Verification Engineer (Bengaluru)
🏢 Sourceright Technologies
📍 Bengaluru