Role Description

Who we are

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

Summary

UST is looking for a SoC Design Verification Engineer with expertise in SystemVerilog, UVM, and functional verification of complex SoC/IP designs.

The Opportunity

We are seeking a motivated SoC Design Verification Engineer to verify complex digital IPs and SoCs across various stages of the development cycle. The ideal candidate will work closely with design, architecture, and validation teams to ensure first-pass silicon success through robust verification methodologies.

Key Responsibilities

- Develop and execute verification plans for IP and SoC-level features
- Create and enhance UVM/SystemVerilog-based verification environments
- Develop testcases, sequences, checkers, assertions, and coverage models
- Perform functional, regression, and system-level verification
- Analyze simulation results and debug RTL/design issues
- Drive coverage closure including code, functional, and assertion coverage
- Collaborate with RTL designers to resolve verification and integration issues
- Participate in design reviews and verification sign-offs
- Support SoC integration, subsystem verification, and silicon bring-up activities

Required Qualifications

- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field
- 2-5 years of experience in SoC/IP Design Verification




- Robust knowledge of SystemVerilog and UVM methodology
- Good understanding of digital design fundamentals, RTL, and computer architecture concepts
- Experience in developing verification environments, testbenches, and regression suites
- Strong debugging skills using simulators such as VCS, Xcelium, or Questa
- Understanding of verification concepts including assertions, coverage, and constrained-random verification
- Familiarity with industry-standard bus protocols such as AXI, AHB, APB, or PCIe
- Good scripting skills in Python, Perl, Tcl, or Shell
- Strong analytical, problem-solving, and communication skills

Preferred Qualifications

- Experience in SoC-level verification and subsystem integration
- Knowledge of ARM-based SoCs and AMBA protocols
- Exposure to Formal Verification and CDC/RDC verification
- Experience with emulation or FPGA-based validation flows
- Familiarity with Git, Jenkins, and verification automation frameworks

Leadership Expectations

- Take ownership of verification deliverables and quality metrics
- Proactively identify corner cases and improve verification coverage
- Collaborate effectively with cross-functional teams
- Drive debug and closure activities with minimal supervision
- Contribute to reusable verification methodologies and best practices.





What We Believe We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do.

Humility We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

Humanity Through business, we will better the lives of those less fortunate than ourselves.

Integrity We honour our commitments and act with responsibility in all our relationships.

Equal Employment Opportunity Statement UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation. All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law. UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.

- To support and promote the values of UST.
- Comply with all Company policies and procedures

Skills vlsi design,design verification,systemverilog,testbench,testing, UVM, SystemVerilog

📌 Associate II - VLSI (Bengaluru)
🏢 UST
📍 Bengaluru