Job DescriptionYour Role: N-Own feasibility studies for defining the system architecture, requirements, and external interfaces; nn Developmicroarchitecture and logic design in collaboration with functional leads to deliver design from architecture to tape-out; n Perform RTL coding, Lint checks, CDC tests, and creating timing constraint files; n Work closelywith Synthesis, STA, PD, and DFT teams to meet all functional requirements, performance, power, and area goals; n Develop flows and tools as necessary in support of design activities. NnYour profile: NWork location: PAN India NNP: Max 45days Nn 8+ year experience in VLSI design; n BSC/MSC in Electrical/Computer engineering; n Solid Verilog/System Verilog or VHDL skills; n Experience in defining microarchitecture and design of complex design units; n SoC design experience; n Proficient in advanced design practices (Lint, CDC, and Low Power Design); n Proficient with the various backend tools (synthesis and STA); n Familiar with CPU (ARM, RISC-V, or x86) instruction set; n Proficiency using Perl/C/Python scripting and programming; n Verificationmethodologies understanding; n Good communication and interpersonal skills. N

📌 Rtl Design Leads/Architect | 9-12yrs (Karnataka)
🏢 Capgemini Engineering
📍 Karnataka