Job DescriptionRTL Design Engineer | 5-12 Years
NWe are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.
NKey Requirements:
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- Strong experiencein RTL design using Verilog/SystemVerilog or VHDL N
- Hands-on experience in ASIC/SoC development N
- Strong understanding ofdigital design concepts, including combinational logic, sequential logic, and FSMs N
- Experience in functional verification and RTL debugging N
- Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC. N
- Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle N

nGood to Have:
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- Exposure to UVM-based verification environments N




- Experience with Python,Perl, or Shell scripting N
- Familiarity with STA and synthesis flows N

nQualification:
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- Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field N

nWhy Join Us?
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- Chance to work on cutting-edge ASIC/SoC technologies N
- Collaborative and fast-paced engineering environment N
- Strong learning and career growth opportunities N
- Competitive compensation and benefits package N

nInterested professionals can forward their resumes to [email protected] for further discussion.

📌 Hiring: Rtl Design Engineer Role (Bengaluru)
🏢 HCLTech
📍 Bengaluru