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RTL DESIGN ENGINEER

THE ROLE:
As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence.

THE PERSON:
We are seeking an enthusiastic and skilled Design Engineer to join the team within AMD’s Adaptive & Embedded Computing Group (AECG). In this role, you will be part of a team responsible for architecting, designing, and verifying critical on-chip debug, instrumentation, and testability deployed across AMD's industry-leading FPGA, Adaptive SoC (Versal, Zynq UltraScale+),



and custom silicon platforms. You will work across both RTL design and functional verification flows, collaborating closely with software, emulation, and silicon bring-up teams.

KEY RESPONSIBILITIES:
• RTL Design & Integration:

• Design, enhance, and integrate digital IP blocks and subsystems using Verilog / SystemVerilog.
• Work on on-chip debug architectures, JTAG/Boundary-Scan controllers (IEEE 1149.1/1500/1687), data movement datapaths, and packetized debug protocols.
• Implement and maintain Vivado IP packaging, parameterization, and timing constraints (XDC/SDC).

• Design Verification:

• Develop and maintain modular, reusable testbenches in SystemVerilog / UVM.
• Write test plans, functional assertions (SVA), and covergroups based on architectural specifications.
• Execute constrained-random verification, analyze code/functional coverage, and root-cause RTL bugs.

• Silicon Validatio

📌 RTL DESIGN ENGINEER (Hyderabad)
🏢 Advanced Micro Devices
📍 Hyderabad