Design Verification CAD Engineer
Location: Bengaluru
Experience: 8–12 Years
Role Overview
We are looking for a Design Verification CAD Engineer to build and optimize verification infrastructure, regression frameworks and automation for large-scale ASIC/SoC programs.
Key Responsibilities
• Own DV infrastructure and regression management for complex SoC/IP verification environments.
• Develop and maintain scalable simulation, regression, coverage and reporting flows.
• Build automation frameworks using Python, Perl and Bash.
• Develop and maintain CI/CD pipelines for verification flows and automated regression.
• Integrate simulation, compilation, regression and coverage tools into automated workflows.
• Monitor regression health, analyze failures and improve debug and triage efficiency.
• Develop dashboards, reports and automation for regression status, coverage and verification metrics.
• Optimize regression infrastructure for scalability, performance and resource utilization.




• Collaborate with Design Verification, RTL, CAD and Infrastructure teams to resolve flow and infrastructure issues.
• Drive methodology improvements and standardization across verification projects.

Required Skills
• 8–12 years of experience in DV CAD / Verification Infrastructure.
• Strong experience in DV infrastructure and regression management.
• Strong scripting/programming skills in Python, Perl and Bash.
• Hands-on experience developing CI/CD flows and automation frameworks.
• Strong understanding of SystemVerilog/UVM-based verification environments.
• Experience with simulation tools such as VCS, Xcelium or Questa.
• Good understanding of Linux/Unix environments, Git and automation workflows.
• Robust debugging, problem-solving and cross-functional collaboration skills.

📌 Design Verification CAD Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru