01 Oct
|
Tsavorite Scalable Intelligence
|
Bengaluru
01 Oct
Tsavorite Scalable Intelligence
Bengaluru
About Company
Tsavorite Scalable Intelligence is building a new foundation for AI computing. We design silicon, systems, and software that work as one, bringing together general-purpose processing, AI acceleration, and scalable memory in a single architecture. From edge devices to data centers, our goal is to make advanced AI more powerful, efficient, and accessible.
Our founding team has a track record of shipping the highest performance silicon and we have engineering teams in the US and India. We are looking for curious, driven people across disciplines who want to turn ambitious engineering into real products and help shape how the world computes.
Job Summary
We are seeking an experienced verification engineer with strong expertise in SystemVerilog/UVM and/or C/C++-based verification to drive the verification of high-speed interconnect and memory IPs for advanced chiplet-based architectures. The ideal candidate will have hands-on experience in IP- and subsystem-level verification, with a strong focus on PCIe, CXL, UCIe, Ethernet, and DDR/memory controller verification.
The role will involve protocol-level validation, coherency, cache and memory systems, and die-to-die communication.
Technical Skills & Expertise
• Strong experience developing UVM-based verification environments from scratch.
• Ability to create comprehensive verification plans and develop testbenches tailored to assigned IP, SubSystem, or functional domain.
• Hands-on experience verifying PCIe, CXL, UCIe, Ethernet, and DDR/memory controller IPs.
• Strong architectural and protocol-level knowledge of UCIe, PCIe, CXL, Ethernet, and DDR IPs, including working knowledge of FDI and RDI interfaces.
• Hands-on experience with industry-standard verification, simulation, and debug tools such as Questa, VCS, and Visualizer.
• Robust experience with constrained-random stimulus, functional coverage, and assertion-based verification methodologies.
• Knowledge of chiplet architectures and die-to-die comm
📌 ASIC Design Verification (Bengaluru)
🏢 Tsavorite Scalable Intelligence
📍 Bengaluru