ASIC Design Verification (Bengaluru)

ASIC Design Verification (Bengaluru)

01 Oct
|
Tsavorite Scalable Intelligence
|
Bengaluru

01 Oct

Tsavorite Scalable Intelligence

Bengaluru

About Company

Tsavorite Scalable Intelligence is building a new foundation for AI computing. We design silicon, systems, and software that work as one, bringing together general-purpose processing, AI acceleration, and scalable memory in a single architecture. From edge devices to data centers, our goal is to make advanced AI more powerful, efficient, and accessible.

Our founding team has a track record of shipping the highest performance silicon and we have engineering teams in the US and India. We are looking for curious, driven people across disciplines who want to turn ambitious engineering into real products and help shape how the world computes.

Job Summary

Design verification engineer working on server class ARM CPU Sub-System verification at block and SoC level. The role involves developing test plans, verification environments, checker/scoreboards, test execution, analysis and debug at Sub-System, chiplet and multi-chiplet level.

Technical Skills & Expertise





• Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with hands-on experience in IP/Sub-System and/or SoC level verification.
• Experience in development of UVM based verification environments from scratch.
• Create verification plans and develop testbenches tailored to assigned IP/Sub-System or functional domain.
• Develop the verification setting and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics.
• Working knowledge on CMN (Coherent Mesh Network), SMMU (System Memory Management Unit), GIC (Generic Interrupt Controller), ARM Chip-to-Chip.
• Expertise in coherency concepts and CHI protocol.
• Hands on expertise and protocol knowledge in any of: CHI/APB/AXI/CXS.
• Knowledge of interaction of CPU Sub-System with high performance NoCs and memory systems.
• Hands on experience doing verification on ARM CPU for server class design.
• Strong architecture domain knowledge in ARM Sub-System (A-cores) including booting and

📌 ASIC Design Verification (Bengaluru)
🏢 Tsavorite Scalable Intelligence
📍 Bengaluru

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