Job description:
TCS has always been in the spotlight for being adept in the next big technologies. What we can offer you is a space to explore wide-ranging technologies and quench your techie soul.
Role Overview
The Static Timing Analysis (STA) Engineer role focuses on timing constraint development, analysis, closure, and signoff for complex ASIC and SoC designs across multiple technology nodes. The role requires strong STA fundamentals, hands-on expertise with industry-standard tools, and close collaboration with RTL, Physical Design, DFT, and Signoff teams.
Core Responsibilities (All Levels)
• Perform static timing analysis using Synopsys PrimeTime or Cadence Tempus
• Develop, validate, and maintain SDC constraints including clocks and exceptions
• Analyze setup/hold, transition, capacitance, and path-based violations
• Support timing closure and ECO implementation with PD teams
• Execute MCMM analysis across PVT corners and modes
• Participate in timing signoff reviews and documentation