Role Description
Who we are:
At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .
Summary
UST is looking for an RTL Design Lead with experience in PCIe Gen5/6
The Opportunity
We are looking for a Lead RTL Design Engineer to drive the architecture, design, and execution of high-performance digital subsystems with a strong focus on PCIe-based designs. This role requires deep expertise in RTL development, protocol understanding, and end-to-end ownership from architecture to validation.
Key Responsibilities
• Own end-to-end RTL design and micro-architecture for PCIe-based subsystems
• Translate system requirements into scalable architecture and RTL implementation
• Design PCIe datapath, control logic, buffering, flow control, and ordering mechanisms
• Develop synthesizable RTL using Verilog
• Lead synthesis,
lint, CDC/RDC, timing analysis and closure
• Drive FPGA/ASIC integration, bring-up, and validation
• Debug PCIe protocol and system-level issues
• Collaborate with verification, validation, and firmware teams
• Lead design reviews, code reviews, and technical sign-offs
• Mentor team members and guide technical execution.
Required Qualifications
• 8-12 years of RTL design experience (FPGA/ASIC)
• Strong expertise in Verilog
• Strong digital design fundamentals (FSMs, FIFOs, pipelines, clock/reset)
• Deep understanding of PCIe protocol (TLPs, LTSSM, flow control, ordering)
• Experience with FPGA tools (Vivado/Quartus)
• Robust experience in synthesis, timing closure, CDC, lint, and debug
• Strong debugging skills across simulation and hardware
• Experience with high-speed interfaces (PCIe, DDR)
Preferred Qualifications
• Familiarity with AXI/APB/AHB, I2C, SPI, UART
• FPGA board
📌 Technical Lead I (Bengaluru)
🏢 UST
📍 Bengaluru