Lead DFT Engineer
Location:

Bangalore
Experience:

8+ Years

Job Description
We are looking for an experienced

Lead DFT Engineer

with strong expertise in Design-for-Test (DFT), ATPG, and MBIST, along with hands-on experience using Cadence tools.

Key Responsibilities
Lead DFT architecture, implementation, and verification for complex SoC designs.
Drive scan insertion, ATPG pattern generation, coverage analysis, and test pattern debugging.
Implement and verify MBIST, memory test architectures, and test controllers.
Perform DFT rule checks (DRC), scan chain analysis, and test coverage optimization.
Collaborate with RTL, Physical Design, and Verification teams to resolve DFT-related issues.
Support DFT sign-off, test pattern validation, and production test readiness.





Must-Have Skills
8+ years of hands-on DFT engineering experience.
Solid expertise in

ATPG and MBIST .
Hands-on experience with

Cadence DFT tools .
Expertise in scan insertion, scan compression, DFT architecture, and test coverage analysis.
Strong debugging, problem-solving, and cross-functional collaboration skills.

Preferred Skills
Experience with full-chip SoC DFT implementation and silicon validation.
Knowledge of JTAG, boundary scan, and IEEE 1500/1687 standards.
Experience supporting DFT sign-off and manufacturing test requirements.

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