Job Description
Lead DFT Engineer
nLocation: Bangalore
nExperience: 8+ Years
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nJob Description
nWe are looking for an experienced Lead DFT Engineer with strong expertise in Design-for-Test (DFT), ATPG, and MBIST, along with hands-on experience using Cadence tools.
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nKey Responsibilities
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- Lead DFT architecture, implementation, and verification for complex SoC designs.n
- Drive scan insertion, ATPG pattern generation, coverage analysis, and test pattern debugging.n
- Implement and verify MBIST, memory test architectures, and test controllers.n
- Perform DFT rule checks (DRC), scan chain analysis, and test coverage optimization.n
- Collaborate with RTL, Physical Design, and Verification teams to resolve DFT-related issues.n
- Support DFT sign-off, test pattern validation, and production test readiness.n

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nMust-Have Skills
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- 8+ years of hands-on DFT engineering experience.n
- Solid expertise in ATPG and MBIST .n
- Hands-on experience with Cadence DFT tools .n
- Expertise in scan insertion, scan compression, DFT architecture, and test coverage analysis.n
- Strong debugging, problem-solving, and cross-functional collaboration skills.n

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nPreferred Skills
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- Experience with full-chip SoC DFT implementation and silicon validation.n
- Knowledge of JTAG, boundary scan, and IEEE 1500/1687 standards.n
- Experience supporting DFT sign-off and manufacturing test requirements.n

📌 Lead DFT Engineer (Bengaluru)
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