01 Oct
|
leadIC Design
|
Vasanth Nagar
01 Oct
leadIC Design
Vasanth Nagar
Experience:
4–10 Years
Location:
Bengaluru
Employment Type:
Full-Time
About the Role
We are looking for an experienced
Memory / Custom Layout Engineer
to join our semiconductor design team and work on advanced
SRAM, ROM, NVM and memory compiler
designs.
The ideal candidate will have strong hands-on experience in
full-custom memory layout , including bitcells, memory arrays, row/column decoders, sense amplifiers, I/O and peripheral circuits. The role will involve working closely with circuit design, physical verification and technology teams to develop
high-quality, area-efficient and silicon-ready layouts
in advanced CMOS/FinFET technologies.
Key Responsibilities
Develop
full-custom layouts
for SRAM, ROM, NVM and memory compiler blocks.
Perform hands-on layout implementation of Bitcells, Memory arrays, Row and column decoders, Sense amplifiers, I/O circuits, Peripheral circuits, Control and supporting logic
Perform
floorplanning, placement and routing
for complex memory blocks.
Develop hierarchical layouts and optimize layouts for
area, performance,
power and manufacturability .
Apply advanced layout techniques for
matching, symmetry, parasitic reduction and noise isolation .
Analyze and optimize layout considering
design rules, device characteristics and technology requirements .
Perform physical verification including DRC, LVS, ERC, Antenna, EM/IR
Debug physical verification issues and work with circuit/physical design teams to resolve them.
Support
post-layout extraction and parasitic-aware optimization .
Work closely with circuit designers to understand layout-critical requirements and achieve desired PPA targets.
Support block-level and top-level
memory integration and tapeout activities .
Contribute to layout methodology, automation and productivity improvements.
Required Skills & Experience
Bachelor's or Master's degree in
ECE, EE, VLSI, Microelectronics
or a related field.
Robust hands-on experience in
Memory Layout / Custom Layout .
📌 Memory Layout Engineer (Vasanth Nagar)
🏢 leadIC Design
📍 Vasanth Nagar