Dft Lead Engineer (Vasanthanagar)

Dft Lead Engineer (Vasanthanagar)

01 Oct
|
BITSILICA
|
Vasanthanagar

01 Oct

BITSILICA

Vasanthanagar

8 to 10+ yrs of experience in DFT architecture, scan Insertion, compression at core level and So C level.
Experience in ATPG pattern generation, coverage analysis
Experience with timing and no-timing simulations
Experience in Memory-BIST
Have understanding of SSN architecture, clock architecture, OCC

📌 Dft Lead Engineer (Vasanthanagar)
🏢 BITSILICA
📍 Vasanthanagar

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