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The Emulation Engineer will be responsible for executing emulation and validation of RTL designs using Verilog, VHDL, and System Verilog. The role requires strong expertise in front-end and back-end flows, RTL debugging, scripting, and pre-silicon validation. You will work closely with cross-functional teams, leveraging industry-standard tools and methods to ensure design accuracy and efficiency. This position is based in Bangalore, requiring 8 to 12 years of experience in emulation and simulation environments.

Job Description

Job Title: Emulation Engineer

Location: Bangalore

Experience Required: 8 to 12 Years

Key Responsibilities:

-
RTL Design and Testbench Development:
- Proficient in Verilog, VHDL, and System Verilog for creating and debugging RTL designs.
- Develop and write testbenches to validate and verify design functionality.

-
Emulation and Simulation Flow:
- Manage front-end and back-end compilation processes for emulation and simulation of complex digital systems.




- Ensure smooth execution of emulation flows from RTL design to hardware validation.

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Debugging:
- Perform comprehensive RTL debugging using advanced techniques such as triggers and System Verilog Assertions (SVA).
- Utilize the Verdi tool for effective debugging and problem resolution.

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Scripting and Automation:
- Develop and maintain automation scripts using Python and TCL to streamline verification and testing processes.

-
Pre-Silicon Validation:
- Execute pre-silicon validation processes, ensuring the integrity and performance of designs before fabrication.

-
Cross-functional Collaboration:
- Work closely with design, verification, and hardware teams to achieve successful emulation and validation outcomes.

-
Problem-solving and Innovation:
- Provide solutions to design challenges, identify bottlenecks in the verification process, and propose enhancements for efficiency.

Designation

emulation Engineer

Key Skills

PythonVerilogVHDL

Indus

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