02 Oct
|
TCS_India
|
Hyderabad
02 Oct
TCS_India
Hyderabad
Develop and execute verification plans for PCIe IP (Controller / PHY / Subsystems).
• Build and maintain UVM/SystemVerilog-based verification environments.
• Write test cases, assertions, and functional coverage models.
• Perform protocol-level verification for PCIe layers:
o Transaction Layer
o Data Link Layer
o Physical Layer
• Debug design issues by analyzing:
o Simulation results
o Waveforms
o Protocol logs
• Work closely with design, architecture, and validation teams to resolve bugs.
• Perform compliance and corner-case testing (LTSSM states, error injection, power management).
• Integrate and verify with VIPs (Verification IP) for PCIe.
• Contribute to regression automation and continuous integration flows.
• Support coverage closure (functional + code coverage).
📌 UVM/System (Hyderabad)
🏢 TCS_India
📍 Hyderabad