Key responsibilities in your recent role
Create Subsystem Verification plan for PMBUS, AVS interface and signoff protocol compliance
Formal verification coverage of critical control interfaces
SV, UVM based Verification environment.
RNM based simulation, Matlab models integration - DPI in Verification strategy.
SOC Integration verification and system level scenarios development
GLS Verification including root causing down to flop level
Code Coverage, functional coverage
Fault Injection Campaign Execution for ASIL-D Products
Familiarity with industry standard protocols like I2C/I3C, UART, AHB/APB, SMBUS, SPI. Mandatory:
Demonstration of AI-driven productivity improvements in Verification test case generation and coverage closure
Should have thrived in fast paced environments in the recent past
In Depth debug and Root cause analysis skills
Your Profile Qualifications and skills to help you succeed
B.E./B.Tech/M.E./M.Tech in Electrical/Electronic Engineering Bachelor's - 4 to 9
In depth understanding of ASIC verification concepts and techniques. Ability to architect complex module / sub system / full chip testbenches and build verification infrastructure in SV/UVM.
Should be a valuable mentor and guide the junior engineers in the team.
Experience in ARM based SoC verification covering RTL, Power Aware and Gate level simulations is a plus.
Valuable knowledge in industry standard protocols is preferable