4 - 8 years of experience in ASIC/SoC/IP Design Verification.
Strong hands-on expertise in SystemVerilog and UVM.
Good understanding of Ethernet MAC architecture and functionality.
Positive understanding of Ethernet PHY / PCS (Physical Coding Sublayer).
Familiarity with Ethernet standards and concepts such as MAC/PCS datapath, packet framing, encoding/decoding, link establishment, and error handling.
Solid experience in developing UVM testbenches, sequences, drivers, monitors, scoreboards, and functional coverage.
Good understanding of constrained-random verification and coverage-driven verification.
Experience with debugging simulation failures and waveform analysis.
Valuable knowledge of RTL design concepts, digital logic, and common on-chip interfaces.
Experience with coverage analysis and closure, including functional and code coverage.
Good scripting/debugging skills using Python, Perl, Tcl, or similar is a plus.

📌 Senior Design Verification Engineer Hyderabad
🏢 Einfochips
📍 Hyderabad