Job Role: PD Engineer (Subsystem / Full chip)

Experience: 7 to 10 Years

Location: Bangalore

Responsibilities
Execute RTL-to-GDSII implementation for complex Compute & Network SoCs/subsystems.
Handle floorplanning, placement, CTS, routing and timing closure .
Drive PPA optimization for performance, power, area and congestion.
Perform STA, SI, IR/EM, antenna and physical verification sign-off.
Drive DRC/LVS and timing/power closure .
Work on multi-voltage, low-power and UPF-based implementation .
Support ECOs, physical sign-off and tape-out .
Collaborate with RTL, DFT, Verification and Architecture teams .

Requirements
7+ years of hands-on experience in ASIC/SoC Physical Design .
Strong experience with Innovus / ICC2, Tempus / PrimeTime, Voltus / RedHawk and Calibre / Pegasus .
Strong knowledge of STA, timing closure, signal integrity,



power and IR/EM analysis .
Experience with advanced nodes – 5nm/4nm/3nm/2nm .
Valuable understanding of multi-clock designs, high-speed interfaces, memories and hierarchical implementation .
Knowledge of DFT, low-power implementation and physical verification .
Robust Tcl/Python/Perl scripting skills for flow automation.
Solid debugging and problem-solving skills with tape-out ownership .

Preferred Skills
Experience with CPU/GPU/NPU, networking processors or switch SoCs .
Exposure to PCIe, Ethernet, SerDes, DDR/HBM and other high-speed interfaces.
Experience in hierarchical/partition-based implementation and advanced-node PPA optimization.

📌 Senior Physical Design Engineer Bengaluru (India)
🏢 Modernize Chip Solutions (MCS)
📍 India