Job Description

SmartSoC, a Virtusa Company, is a leading semiconductor engineering services organization specializing in end-to-end ASIC, SoC, FPGA, Embedded Systems, and VLSI design solutions. Backed by Virtusa's global engineering capabilities, SmartSoC partners with leading semiconductor companies to deliver innovative, high-quality silicon solutions across the entire chip development lifecycle.

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Looking For : STA Lead

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Work Location: Bangalore

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Experience: 3 to 10 Years

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Availability: Immediate or currently serving notice candidates is preferred

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Key Responsibilities:

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Timing Closure Leadership: Deliver sign-off quality STA across complex, high-frequency designs, ensuring robust performance in diverse modes and corners.
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Customer Impact: Translate technical excellence into measurable outcomes for customers — faster turnaround, improved QoR, and optimized PPA trade-offs.
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Constraint Development: Architect and validate timing constraints to guarantee design reliability and seamless integration into customer workflows.
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Synthesis & Optimization: Own synthesis flows using Fusion Compiler and Design Compiler, achieving customer-defined targets for timing, area, and power.
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Cross-functional Collaboration:



Partner with RTL, PD, and DFT teams to proactively resolve design challenges, ensuring smooth delivery for customer programs.
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AI-driven Design: Apply reinforcement learning tools (DSO.ai) to accelerate design space exploration, delivering cutting-edge solutions that reduce cycle time.
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Low Power & UPF: Implement and verify UPF-based power intent, ensuring energy-productive designs aligned with customer requirements.
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Formal Equivalence & ECOs: Guarantee functional correctness through formal verification and ECO generation, enabling reliable customer tape-outs.
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Qualifications:

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Bachelor's degree in Electrical Engineering from reputed universities
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3+ years of semiconductor design experience at leading companies
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Expertise in STA, synthesis, constraints, and low-power verification.
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Proficiency in industry-standard tools: PrimeTime, Fusion Compiler, Design Compiler, Formality, ICC2, Conformal, VCLP.
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Robust programming skills in TCL, Python, Perl, and Verilog.
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Deep understanding of advanced node challenges (cross talk, OCV, AOCV, POCV) and clock architectures.
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📌 Senior Pd Sta Engineer Bengaluru (India)
🏢 SmartSoC Solutions
📍 India