Job Description

Lead STA & Synthesis Engineer

n

Location: Bengaluru

n

Experience: 8–12 Years

n

Role Overview

n

We are looking for a Lead STA & Synthesis Engineer with robust hands-on expertise in Static Timing Analysis, RTL Synthesis, timing closure, and implementation flows for complex SoC designs.

n

Key Responsibilities

n

n
Own RTL-to-gate synthesis and timing analysis for complex SoC/IP designs.
n
Drive STA, timing constraints, and timing closure across MCMM/MMC scenarios.
n
Develop, validate, and debug SDC constraints, clocks, exceptions, and timing paths.
n
Perform setup/hold analysis, critical path analysis, and timing optimization.
n
Work closely with RTL, Physical Design, DFT, and implementation teams to resolve timing issues.
n
Analyze and optimize area, power, and performance (PPA) during synthesis.
n
Drive ECOs and timing fixes through implementation and signoff.
n
Debug synthesis/STA issues including unconstrained paths, false paths,



clock interactions, and constraint violations.
n
Develop scripts and automation using Tcl/Python/Perl to improve flow efficiency.
n

n

Core Technical Requirements

n

n
8–12 years of experience in STA, synthesis, or front-end implementation.
n
Strong expertise in Synopsys Design Compiler / Fusion Compiler or equivalent synthesis tools.
n
Solid hands-on experience with Synopsys PrimeTime or equivalent STA tools.
n
Deep understanding of SDC, MCMM/MMC, setup/hold, clocking, OCV/AOCV/POCV, and timing exceptions.
n
Experience with RTL synthesis, timing optimization, and ECO flows.
n
Robust understanding of ASIC/SoC implementation and signoff methodologies.
n
Proficiency in Tcl/Python/Perl scripting.
n
Experience with advanced technology nodes and complex SoC designs is preferred.
n

n

📌 Lead Sta & Synthesis Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru