Analog and Design verification (Hyderabad)

Analog and Design verification (Hyderabad)

02 Oct
|
Acesoft Labs
|
Hyderabad

02 Oct

Acesoft Labs

Hyderabad

Role & responsibilities

Bachelors with 2+ years of work experience or Post Graduate Degree in Electronics Engineering or related engineering field with 1-2 years of working experience is required.

Description:

- Good knowledge of Basic Analog/Digital concepts.

- Good knowledge of Verilog/SV concepts.

- Experience in using spice simulation and digital simulation tools like Virtuoso, primesim, Finseim, Hspice, Xcellium, Simvision, Waveview.

- Experience in understanding Spice simulation workplace/Digital simulation environment, able to debug analog/digital design related issues.

- Work experience in co-sim simulation designs is a plus.

- Good scripting skills using perl, python is a plus.

- Must possess good communication skills and ability to work well in a team.

Preferred candidate profile

Exp: 1 - 3 years

Location: HYD

Immediate joiner

Thanks & Regards

M Jeevan, Kalyan

,

,

📌 Analog and Design verification (Hyderabad)
🏢 Acesoft Labs
📍 Hyderabad

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