Job Title - Senior Physical Design Engineer ASIC / VLSI

Job Description

We are hiring a Senior Physical Design Engineer to work on processors, controller architectures, and ASICs. The role involves endtoend physical design ownership, including floor planning, timing closure, physical verification, and tapeout support on advanced technology nodes with TSMC.

Key Responsibilities

- Blocklevel physical design implementation for ASICs
- Lowpower aware floor planning, placement, CTS, routing, and RC extraction
- STA timing closure at block level
- Perform IR/EM analysis and resolve power integrity issues
- Physical verification closure using DRC, LVS, ERC, Antenna checks
- Work closely with design, STA, and verification teams
- Support signoff and tapeout activities

Mandatory Skills

- 58 years of experience in Physical Design / APR implementation
- Strong experience with advanced nodes (6nm / 7nm preferred)




- Expertise in Cadence P&R; tools – Innovus, Tempus
- Robust knowledge of STA timing closure
- Handson experience with Calibre DRC/LVS/Antenna
- Experience in IR/EM analysis and closure
- Strong fundamentals in digital electronics and microprocessors

Preferred Skills

- APR flow development & PPA optimization
- Formal verification exposure
- Strong verbal communication skills

Education

- Bachelor’s or Master’s degree in Electronics / VLSI / Computer Architecture

Key Skills -

Physical Design, ASIC, APR, Floorplanning, Placement, CTS, Routing, STA, Timing Closure, IR/EM, DRC, LVS, Calibre, Innovus, Tempus, 6nm, 7nm, Low Power Design, Digital Electronics, Tapeout

📌 Physical Design Engineer (Hyderabad)
🏢 Acesoft Labs
📍 Hyderabad