1. System-on-Chip (SoC) Design Verification Engineer

Location: Bangalore, India

Experience Level: 5+ Years

Notice Period: 030 Days (Immediate Joiners Preferred)

Role Overview

We are seeking an experienced Design Verification Lead to join our semiconductor team in Bangalore. In this role, you will lead complex SoC verification environments, perform root-cause debugging, and drive coverage closure to ensure functional correctness prior to tape-out.

Key Responsibilities

- Develop and maintain scalable, UVM-based verification environments at the SoC level.
- Drive complete functional and code coverage closure using modern metrics and tools.
- Perform complex debug sessions at the chip level, isolating issues across hardware, testbenches, and firmware interfaces.
- Collaborate closely with architecture, RTL design, and synthesis teams to refine verification plans.

Required Qualifications

- 5+ years of direct experience in SoC Design Verification (DV).
- Robust hands-on experience in debugging complex multi-block SoC testbenches.
- Deep knowledge of Coverage Closure strategies (SystemVerilog Assertions, Functional Coverage, Code Coverage).
- Proficiency in SystemVerilog, UVM, and scripting languages (Python, Perl, or TCL).

📌 Senior Design Verification Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru