High-Speed Protocol DV Engineer (PCIe Specialist)

Location: Bangalore, India

Experience Level: 5 to 13 Years

Notice Period: 030 Days

Role Overview

We are hiring a Senior/Lead Design Verification Engineer with deep expertise in high-speed serial interface protocols, specifically PCIe. You will be responsible for verification strategy, testbench architecture, and ensuring protocol compliance.

Key Responsibilities

- Design and implement UVM-based testbenches and VIP integration for PCIe controllers/subsystems.
- Create comprehensive test plans covering protocol link training, power states, and throughput stress testing.
- Perform Gate-Level Simulations (GLS) including timing checks, SDF back-annotation, and X-propagation analysis.
- Drive debug efforts for complex protocol-level failures and timing violations.

Required Qualifications

- 5 to 13 years of Design Verification experience in complex ASIC/SoC projects.
- Direct, hands-on experience verifying PCIe controllers or PHY interfaces.
- Solid working knowledge of Gate-Level Simulation (GLS) debug flow and setup.
- Expert command of SystemVerilog, UVM, and industry-standard simulators (VCS, Questa, or Xcelium).

📌 Senior Design Verification Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru