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The Role

We at AECG SSD Custom Silicon are seeking a highly motivated and experienced Full-Chip Floorplan Engineer to drive physical implementation planning for complex SoCs and ASICs. The candidate will be responsible for developing and optimizing full-chip floorplans, partitioning strategies, power planning, interconnect planning, and physical architecture to achieve aggressive PPA (Power, Performance, Area) targets while ensuring design convergence and manufacturability.

The role requires close collaboration with Architecture, RTL,



Physical Design, DFT, Power, Package, and Verification teams throughout the SoC development lifecycle. Industry full-chip floorplanning activities commonly include die shaping, macro placement, IO planning, power-domain planning, pin assignment, feedthrough planning, and physical integration strategy development.

The Person

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

Key Responsiblities

• Full-Chip Floorplanning
• Develop and own top-level SoC floorplan architecture.
• Define chip aspect ratio, die size, partitioning strategy, and hierarchy planning.
• Perform macro placement and optimization for timing, congestion, power, and thermal considerations.
• Drive floorplan refinement through design milestones.
• Define floorplan topology for large-scale

📌 Lead Full Chip Floorplan Design Engineer (Bengaluru)
🏢 AMD
📍 Bengaluru