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Your roleKey responsibilities in your recent role
As
an engineer, Timing Closure, and Constraints Coding/Validation Engineer, you
will own the architectural timing intent, constraint hygiene, and complete
timing sign-off for complex, multi-million gate SoCs. You will drive multi-mode
multi-corner (MMMC) timing closure from block-level implementation up to
full-chip integration. A core focus of this role is using advanced optimization
tools to fix critical setup, hold, transition and crosstalk violations across
both functional and complex DFT modes (Scan, At-Speed, MBIST etc).
• Timing Closure & ECO Sign-off: Lead and execute block-level and full-chip flat/hierarchical timing closure across advanced process nodes. Generate engineering change orders (ECOs) to fix setup, hold, max transition, and signal integrity violations
• Tool-Driven Optimization: Demonstrate expert mastery over automated ECO fixing tools (Tweaker, PT DMSA/Primeclosure, Cadence Tempus)



drive rapid convergence of complex bottleneck violation
• Multi-Signoff STA Infrastructure: Architect, set up, and execute robust MMMC sign-off environments using Synopsys PrimeTime (PT/PT-PX) and Cadence Tempus. Ensure complete correlation across different timing engines
• Hierarchical Constraint Management: Architect, generate, and maintain clean SDC files at both the Block/IP level and the Full-Chip Top level. Manage constraint promotion, demotion, and validation
• Signal Integrity & Noise Analysis: Strong understanding of crosstalk-induced noise, glitch propagation, signal electromigration (Signal EM), and managing reconvergent timing paths affected by crosstalk delay
• DFT Mode Timing Validation: Define, audit, and validate constraints across multiple operational modes, specifically targeting Scan Shift & Capture, At-Speed Testing, Memory BIST (MBIST), and Logic BIST (LBIST) concurrent execution modes
• Cross-Functional Leadership: C

📌 Principal Engineer Design (Bengaluru)
🏢 infineon
📍 Bengaluru