Principal Synthesis, STA Engineer (Bengaluru)

Principal Synthesis, STA Engineer (Bengaluru)

02 Oct
|
Analog Devices
|
Bengaluru

02 Oct

Analog Devices

Bengaluru

About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

P5 Synthesis & STA Engineer

About the Role
As a P5 Synthesis & STA Engineer, you will provide technical leadership for Synthesis, STA, and timing closure of complex high-performance SoCs with large digital and analog interfaces.
You will drive full-chip timing analysis and closure for complex, multi-GHz SoC, establish robust top-down closure methodologies, and solve complex QoR challenges spanning RTL, synthesis, constraints, clocking, and physical implementation.



The role requires deep hands-on expertise combined with the ability to influence implementation strategy, introduce industry best practices, drive methodology improvements, and mentor engineers into leadership roles.

Key Responsibilities
• Lead and own Synthesis and STA closure for complex, high-performance, multi-GHz SoCs across IP, subsystem, partition, and full-chip levels.
• Develop, validate, and review complex timing constraints spanning IP, subsystem, partition, and full-chip hierarchies.
• Drive full-chip timing signoff across multi-mode, multi-corner scenarios and establish a robust top-down timing closure methodology, driving constraints, budgets, interface timing, and convergence from full-chip to subsystem and partition levels.
• Demonstrate solid expertise in AOCV/SOCV methodologies, variation-aware timing analysis, and advanced-node timing signoff.
• Drive top-level clock planning and balancing across partition

📌 Principal Synthesis, STA Engineer (Bengaluru)
🏢 Analog Devices
📍 Bengaluru

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