DDR PHY Senior Lead Digital Design Engineer (Bengaluru)

DDR PHY Senior Lead Digital Design Engineer (Bengaluru)

02 Oct
|
Qualcomm
|
Bengaluru

02 Oct

Qualcomm

Bengaluru

Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering,



or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

Role Overview
We are seeking a motivated and technically robust DDR PHY Digital Design Engineer to join our team working on next-generation memory interface IPs. The candidate will be responsible for the architecture, RTL implementation, verification support, synthesis, low-power design, DFT, and silicon bring-up of high-performance DDR PHY solutions used in leading-edge SoC products.
Responsibilities
• Design and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces.
• Participate in micro-architecture definition, RTL coding, integration, and debug of complex digital IPs.
• Drive RTL quality and signoff through lint, clock-domain crossing (CDC), reset-domain crossing (RDC), low-power, and design rule checks.
• Collaborate with the functional verification team to develop

📌 DDR PHY Senior Lead Digital Design Engineer (Bengaluru)
🏢 Qualcomm
📍 Bengaluru

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